You will be in charge of defining new product lines of Menta’s embedded FPGA IPs and you will be responsible for the development of the corresponding architectures. The candidate must have a strong expertise in FPGA, routing networks, switchboxes, Look-Up-Table architectures and configuration logic optimization.
Menta has developed a suite of tools and test suites that allow fast and easy exploration of various architectures – while taking into account the specificities of designing an ASIC IP. It is a unique opportunity to apply and expand a FPGA design expertise to the IP world.
The candidate will have a central role within the organization, working with the software team, the physical implementation team, the business development team and the top management.
Desired skills and experience
- MS or a PhD in Electrical Engineering, Computer Science Mathematics or related discipline
- At least 5 years of experience in FPGA architecture development within a FPGA company or in a dedicated R&D team
- Experience in SoC / ASIC design is a plus
- Good skill on RTL languages: VHDL and Verilog
- Good analytical and problem-solving skills
- Solid team player
- Good written and spoken English is mandatory
The candidate will work in a dynamic environment and will get to work with teams from different technical areas in which new creative and innovative ideas will be much appreciated
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