You will lead, grow and support Menta’s highly qualified Digital IC physical implementation team. You will be responsible of/drive the definition, development and verification of the eFPGA IPs to bring them into production, from synthesis to GDSII. You will continuously look for opportunities to improve physical implementation methodologies and flows. You’re a natural team lead and like helping others to be at their best. The team is also handling DfT implementation and verification. You will also handle the management of EDA licenses.
This is a challenging position and an opportunity to work within a highly qualified team that is growing. You will get the chance to work on one of the most exciting new semiconductor products and on the most advanced process nodes (from 180nm to 5nm and beyond).
Desired skills and experience
- 10+ years of hands-on experience in digital physical implementation
- Experience leading physical implementation teams
- You have a very good vision of the entire digital ASIC design flow from synthesis to GDSII
- In depth knowledge of digital back-end EDA tool flows. Knowledge of Synopsys tool (ICC, ICC2, Primetime, StarRC, etc.) is a must. Knowledge of Mentor Graphics Calibre is a plus. Knowledge of Cadence digital flow is a plus.
- Experience on advanced technology nodes, such as 16nm and below is required
- Experience with make files and scripting languages such as Tcl, Python and bash
- Experience at IP level and IP integration at top level are a plus
- FPGAs architecture and FPGAs software knowledge are a plus
- Technical background in RTL design (VHDL, Verilog, SystemVerilog) and/or RTL synthesis is a plus
- Good analytical and problem-solving skills
- Solid team player and leadership skills
- Good written and spoken English is mandatory
- MSc or PhD in Electrical Engineering or equivalent
The candidate will work in a dynamic environment and will get to work with teams from different technical areas in which new creative and innovative ideas will be much appreciated
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